Discussion:
[Linuxptp-devel] Testing PTP on Nios II softcore FPGA system
Jeroen Van den Keybus
2013-03-18 21:28:19 UTC
Permalink
Hi,


I want to run linuxptp on an Altera Nios II embedded FPGA system running
uClinux (-mmu). I use the OpenCores MAC (ethoc), and I have created a PHC
in the FPGA. I intend to do hardware timestamping using this PHC in the
MAC, but for now (to reduce amount of systems to debug concurrently), I
take snapshots of the PHC counter, much the way software timestamping
normally does.

I managed to build and run ptp4l on the embedded system. I also built
testptp to check the correct registration of the PHC, as well as the
required methods to set, get and adjust it.

The problem is: I have only one board and I must therefore test with
another ptp4l running on a regular PC. I have no idea of what to expect of
such a setup (and whether mixed hw/sw timestamp based synchronization works
at all). Are there any obvious problems visible from the log below ? I any
case, the embedded system does get the PC's real time clock.

I'm also curious to know what 'foreign master not using PTP timescale'
means.
I think all delays are in ns and all freqs are ppb. RIght ?


I run ptp4l on the PC as a master:

#> ./ptp4l -i eth0 -S -m
ptp4l[173817.679]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[173817.679]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[173823.679]: port 1: LISTENING to MASTER on
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES


The Nios II embedded system is the slave:

#> root:/> ptp4l -i eth0 -s -m
ptp4l[62.545]: selected /dev/ptp0 as PTP clock
ptp4l[62.584]: failed to read out the clock frequency adjustment: Operation
not supported
ptp4l[62.621]: driver changed our HWTSTAMP options
ptp4l[62.631]: tx_type 1 not 1
ptp4l[62.639]: rx_filter 14 not 12
ptp4l[62.647]: driver rejected most general HWTSTAMP filter
ptp4l[62.656]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[62.668]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[64.053]: port 1: new foreign master e8039a.fffe.e874ae-1
ptp4l[68.056]: selected best master clock e8039a.fffe.e874ae
ptp4l[68.064]: foreign master not using PTP timescale
ptp4l[68.072]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[69.101]: master offset -1363641043689335015 s0 freq +0 path
delay 74154
ptp4l[69.748]: negative path delay -17255
ptp4l[69.756]: path_delay = (t2 - t3) + (t4 - t1)
ptp4l[69.764]: t2 - t3 = -647318253
ptp4l[69.773]: t4 - t1 = +647283742
ptp4l[69.781]: c1 0
ptp4l[69.788]: c2 0
ptp4l[69.796]: c3 0
ptp4l[70.102]: master offset -1363641043688843796 s1 freq +490992 path
delay 28449
ptp4l[71.102]: master offset 19059 s2 freq +510051 path delay 28449
ptp4l[71.111]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[72.103]: master offset -14053 s2 freq +482657 path delay 57637
ptp4l[73.103]: master offset 7596 s2 freq +500090 path delay 57637
ptp4l[74.104]: master offset -20750 s2 freq +474023 path delay 88772
ptp4l[75.104]: master offset 6449 s2 freq +494997 path delay 92379
ptp4l[76.105]: master offset 211224 s2 freq +701706 path delay 94989
ptp4l[77.105]: master offset -179628 s2 freq +374222 path delay 94989
ptp4l[78.106]: master offset 155312 s2 freq +655273 path delay 94614
ptp4l[79.107]: master offset -199269 s2 freq +347286 path delay 94614
ptp4l[80.107]: master offset 71578 s2 freq +558352 path delay 95881
ptp4l[81.108]: master offset -121382 s2 freq +386865 path delay 118887
ptp4l[82.108]: master offset 28629 s2 freq +500462 path delay 118887
ptp4l[83.109]: master offset -508 s2 freq +479914 path delay 122236
ptp4l[84.109]: master offset 16825 s2 freq +497094 path delay 123308
ptp4l[85.110]: master offset 24409 s2 freq +509726 path delay 125638
ptp4l[86.110]: master offset 19511 s2 freq +512150 path delay 125638
ptp4l[87.111]: master offset 209233 s2 freq +707726 path delay 128725
ptp4l[88.111]: master offset -208994 s2 freq +352269 path delay 145758
ptp4l[89.112]: master offset 140780 s2 freq +639344 path delay 145758
ptp4l[90.113]: master offset -205253 s2 freq +335545 path delay 158202
ptp4l[91.113]: master offset 123733 s2 freq +602955 path delay 153801
ptp4l[92.114]: master offset -147200 s2 freq +369142 path delay 171353
ptp4l[93.114]: master offset 81749 s2 freq +553931 path delay 171353
ptp4l[94.115]: master offset -67407 s2 freq +429300 path delay 175381
ptp4l[95.115]: master offset 9056 s2 freq +485541 path delay 171565
ptp4l[96.116]: master offset 30653 s2 freq +509855 path delay 170067
ptp4l[97.116]: master offset 28505 s2 freq +516903 path delay 170067
ptp4l[98.117]: master offset 21351 s2 freq +518300 path delay 166661
ptp4l[99.117]: master offset 20581 s2 freq +523935 path delay 151631
ptp4l[100.118]: master offset 197790 s2 freq +707319 path delay
151631
ptp4l[101.118]: master offset -205466 s2 freq +363400 path delay
159896
ptp4l[102.119]: master offset 130857 s2 freq +638083 path delay
163182
ptp4l[103.120]: master offset -211709 s2 freq +334774 path delay
171204
ptp4l[104.120]: master offset 101529 s2 freq +584499 path delay
171204
ptp4l[105.121]: master offset -118220 s2 freq +395209 path delay
167163
ptp4l[106.121]: master offset 30633 s2 freq +508596 path delay
167163
ptp4l[107.122]: master offset -16606 s2 freq +470547 path delay
169698
ptp4l[108.122]: master offset 17231 s2 freq +499402 path delay
168885
ptp4l[109.123]: master offset 26115 s2 freq +513455 path delay
166467
ptp4l[110.123]: master offset 38850 s2 freq +534025 path delay
146533
ptp4l[111.124]: master offset 210436 s2 freq +717266 path delay
131938
ptp4l[112.125]: master offset -184160 s2 freq +385801 path delay
136728
ptp4l[113.125]: master offset 131022 s2 freq +645735 path delay
130550
ptp4l[114.126]: master offset -210972 s2 freq +343047 path delay
130550
ptp4l[115.126]: master offset 59024 s2 freq +549752 path delay
125570
ptp4l[116.127]: master offset -97518 s2 freq +410917 path delay
132504
ptp4l[117.127]: master offset 33583 s2 freq +512763 path delay
132504
ptp4l[118.128]: master offset -17169 s2 freq +472085 path delay
135985
ptp4l[119.128]: master offset 18387 s2 freq +502491 path delay
134886
^Cptp4l[120.115]: caught signal 2


Jeroen.
Jacob Keller
2013-03-18 21:47:58 UTC
Permalink
Post by Jeroen Van den Keybus
Hi,
I want to run linuxptp on an Altera Nios II embedded FPGA system running
uClinux (-mmu). I use the OpenCores MAC (ethoc), and I have created a
PHC in the FPGA. I intend to do hardware timestamping using this PHC in
the MAC, but for now (to reduce amount of systems to debug
concurrently), I take snapshots of the PHC counter, much the way
software timestamping normally does.
I managed to build and run ptp4l on the embedded system. I also built
testptp to check the correct registration of the PHC, as well as the
required methods to set, get and adjust it.
The problem is: I have only one board and I must therefore test with
another ptp4l running on a regular PC. I have no idea of what to expect
of such a setup (and whether mixed hw/sw timestamp based synchronization
works at all). Are there any obvious problems visible from the log below
? I any case, the embedded system does get the PC's real time clock.
I'm also curious to know what 'foreign master not using PTP timescale'
means.
I think all delays are in ns and all freqs are ppb. RIght ?
#> ./ptp4l -i eth0 -S -m
ptp4l[173817.679]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[173817.679]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[173823.679]: port 1: LISTENING to MASTER on
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES
#> root:/> ptp4l -i eth0 -s -m
ptp4l[62.545]: selected /dev/ptp0 as PTP clock
Operation not supported
ptp4l[62.621]: driver changed our HWTSTAMP options
ptp4l[62.631]: tx_type 1 not 1
ptp4l[62.639]: rx_filter 14 not 12
ptp4l[62.647]: driver rejected most general HWTSTAMP filter
ptp4l[62.656]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[62.668]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[64.053]: port 1: new foreign master e8039a.fffe.e874ae-1
ptp4l[68.056]: selected best master clock e8039a.fffe.e874ae
ptp4l[68.064]: foreign master not using PTP timescale
ptp4l[68.072]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[69.101]: master offset -1363641043689335015 s0 freq +0 path
delay 74154
ptp4l[69.748]: negative path delay -17255
ptp4l[69.756]: path_delay = (t2 - t3) + (t4 - t1)
ptp4l[69.764]: t2 - t3 = -647318253
ptp4l[69.773]: t4 - t1 = +647283742
ptp4l[69.781]: c1 0
ptp4l[69.788]: c2 0
ptp4l[69.796]: c3 0
ptp4l[70.102]: master offset -1363641043688843796 s1 freq +490992 path
delay 28449
ptp4l[71.102]: master offset 19059 s2 freq +510051 path delay 28449
ptp4l[71.111]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[72.103]: master offset -14053 s2 freq +482657 path delay 57637
ptp4l[73.103]: master offset 7596 s2 freq +500090 path delay 57637
ptp4l[74.104]: master offset -20750 s2 freq +474023 path delay 88772
ptp4l[75.104]: master offset 6449 s2 freq +494997 path delay 92379
ptp4l[76.105]: master offset 211224 s2 freq +701706 path delay 94989
ptp4l[77.105]: master offset -179628 s2 freq +374222 path delay 94989
ptp4l[78.106]: master offset 155312 s2 freq +655273 path delay 94614
ptp4l[79.107]: master offset -199269 s2 freq +347286 path delay 94614
ptp4l[80.107]: master offset 71578 s2 freq +558352 path delay 95881
ptp4l[81.108]: master offset -121382 s2 freq +386865 path delay 118887
ptp4l[82.108]: master offset 28629 s2 freq +500462 path delay 118887
ptp4l[83.109]: master offset -508 s2 freq +479914 path delay 122236
ptp4l[84.109]: master offset 16825 s2 freq +497094 path delay 123308
ptp4l[85.110]: master offset 24409 s2 freq +509726 path delay 125638
ptp4l[86.110]: master offset 19511 s2 freq +512150 path delay 125638
ptp4l[87.111]: master offset 209233 s2 freq +707726 path delay 128725
ptp4l[88.111]: master offset -208994 s2 freq +352269 path delay 145758
ptp4l[89.112]: master offset 140780 s2 freq +639344 path delay 145758
ptp4l[90.113]: master offset -205253 s2 freq +335545 path delay 158202
ptp4l[91.113]: master offset 123733 s2 freq +602955 path delay 153801
ptp4l[92.114]: master offset -147200 s2 freq +369142 path delay 171353
ptp4l[93.114]: master offset 81749 s2 freq +553931 path delay 171353
ptp4l[94.115]: master offset -67407 s2 freq +429300 path delay 175381
ptp4l[95.115]: master offset 9056 s2 freq +485541 path delay 171565
ptp4l[96.116]: master offset 30653 s2 freq +509855 path delay 170067
ptp4l[97.116]: master offset 28505 s2 freq +516903 path delay 170067
ptp4l[98.117]: master offset 21351 s2 freq +518300 path delay 166661
ptp4l[99.117]: master offset 20581 s2 freq +523935 path delay 151631
ptp4l[100.118]: master offset 197790 s2 freq +707319 path delay
151631
ptp4l[101.118]: master offset -205466 s2 freq +363400 path delay
159896
ptp4l[102.119]: master offset 130857 s2 freq +638083 path delay
163182
ptp4l[103.120]: master offset -211709 s2 freq +334774 path delay
171204
ptp4l[104.120]: master offset 101529 s2 freq +584499 path delay
171204
ptp4l[105.121]: master offset -118220 s2 freq +395209 path delay
167163
ptp4l[106.121]: master offset 30633 s2 freq +508596 path delay
167163
ptp4l[107.122]: master offset -16606 s2 freq +470547 path delay
169698
ptp4l[108.122]: master offset 17231 s2 freq +499402 path delay
168885
ptp4l[109.123]: master offset 26115 s2 freq +513455 path delay
166467
ptp4l[110.123]: master offset 38850 s2 freq +534025 path delay
146533
ptp4l[111.124]: master offset 210436 s2 freq +717266 path delay
131938
ptp4l[112.125]: master offset -184160 s2 freq +385801 path delay
136728
ptp4l[113.125]: master offset 131022 s2 freq +645735 path delay
130550
ptp4l[114.126]: master offset -210972 s2 freq +343047 path delay
130550
ptp4l[115.126]: master offset 59024 s2 freq +549752 path delay
125570
ptp4l[116.127]: master offset -97518 s2 freq +410917 path delay
132504
ptp4l[117.127]: master offset 33583 s2 freq +512763 path delay
132504
ptp4l[118.128]: master offset -17169 s2 freq +472085 path delay
135985
ptp4l[119.128]: master offset 18387 s2 freq +502491 path delay
134886
^Cptp4l[120.115]: caught signal 2
Jeroen.
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That log looks fine to me. I am also not quite sure what PTP TIMESCALE
is, so would be interested to hear comments on what that warning means.

Otherwise, that looks as I would expect,a lthough the constant + then -
seems ilke it could be an issue.

Though it could just be fluctuating around the converge point, as the
clocks aren't accurate enough to get lower.

Nothing seems incredibly broken though, and obviously using software
timestamping at all will decrease the accuracy and precision. But this
doesn't look horribly wrong.

- Jake
Richard Cochran
2013-03-19 18:51:15 UTC
Permalink
Post by Jacob Keller
That log looks fine to me. I am also not quite sure what PTP TIMESCALE
is, so would be interested to hear comments on what that warning means.
It just means that the master has not set the PTP_TIMESCALE flag. This
happens, for example, when the master is using a UTC system time
(which is what you get using SW timestamping).

If the PTP_TIMESCALE flag is set, then you know that the master's
timescale is TAI. If it isn't set, we just assume UTC, but we really
don't know for sure.

HTH,
Richard
Jeroen Van den Keybus
2013-03-23 21:42:12 UTC
Permalink
Post by Richard Cochran
It just means that the master has not set the PTP_TIMESCALE flag. This
happens, for example, when the master is using a UTC system time
(which is what you get using SW timestamping).
If the PTP_TIMESCALE flag is set, then you know that the master's
timescale is TAI. If it isn't set, we just assume UTC, but we really
don't know for sure.
So it could be prone to shifts due to leap second events ?

Anyway, I have an experimental hardware timestamping on the OpenCores MAC
(first bit of packet at MII level; we use DP83849 dual PHYs which do not
have TS facilities). I also have 2 boards now. Since I bothered you with
the results of the software (board - PC) timestamping, I think you ought to
be given this data as well.

Rgds,

J.


MASTER:

root:/> ptp4l -i eth0 -m
ptp4l[170.299]: selected /dev/ptp0 as PTP clock
ptp4l[170.337]: failed to read out the clock frequency adjustment:
Operation not supported
ptp4l[170.371]: driver changed our HWTSTAMP options
ptp4l[170.379]: tx_type 1 not 1
ptp4l[170.385]: rx_filter 14 not 12
ptp4l[170.391]: driver rejected most general HWTSTAMP filter
ptp4l[170.398]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[170.408]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[176.400]: port 1: LISTENING to MASTER on
ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES


SLAVE:

root:/> ptp4l -i eth0 -m -s
ptp4l[500.635]: selected /dev/ptp0 as PTP clock
ptp4l[500.672]: failed to read out the clock frequency adjustment:
Operation not supported
ptp4l[500.706]: driver changed our HWTSTAMP options
ptp4l[500.714]: tx_type 1 not 1
ptp4l[500.720]: rx_filter 14 not 12
ptp4l[500.726]: driver rejected most general HWTSTAMP filter
ptp4l[500.733]: port 1: INITIALIZING to LISTENING on INITIALIZE
ptp4l[500.744]: port 0: INITIALIZING to LISTENING on INITIALIZE
ptp4l[501.183]: port 1: new foreign master 020123.fffe.45678a-1
ptp4l[505.185]: selected best master clock 020123.fffe.45678a
ptp4l[505.191]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE
ptp4l[507.583]: master offset -7092 s0 freq +0 path delay
46726
ptp4l[508.587]: master offset -7057 s1 freq +35 path delay
46554
ptp4l[509.590]: master offset 2510 s2 freq +2545 path delay
46554
ptp4l[509.596]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED
ptp4l[510.592]: master offset 1995 s2 freq +2783 path delay
46554
ptp4l[511.596]: master offset 2498 s2 freq +3884 path delay
46475
ptp4l[512.598]: master offset 839 s2 freq +2975 path delay
46541
ptp4l[513.601]: master offset -66 s2 freq +2321 path delay
46613
ptp4l[514.605]: master offset 117 s2 freq +2485 path delay
46587
ptp4l[515.608]: master offset -69 s2 freq +2334 path delay
46642
ptp4l[516.611]: master offset -735 s2 freq +1647 path delay
46658
ptp4l[517.614]: master offset 578 s2 freq +2740 path delay
46658
ptp4l[518.617]: master offset 251 s2 freq +2586 path delay
46620
ptp4l[519.619]: master offset -794 s2 freq +1616 path delay
46643
ptp4l[520.623]: master offset 578 s2 freq +2750 path delay
46573
ptp4l[521.627]: master offset 367 s2 freq +2712 path delay
46577
ptp4l[522.629]: master offset 148 s2 freq +2604 path delay
46585
ptp4l[523.631]: master offset -653 s2 freq +1847 path delay
46599
ptp4l[524.635]: master offset 287 s2 freq +2591 path delay
46599
ptp4l[525.638]: master offset 65 s2 freq +2455 path delay
46588
ptp4l[526.641]: master offset -625 s2 freq +1785 path delay
46586
ptp4l[527.647]: master offset 298 s2 freq +2520 path delay
46559
ptp4l[528.647]: master offset 20 s2 freq +2332 path delay
46537
ptp4l[529.650]: master offset 398 s2 freq +2716 path delay
46617
ptp4l[530.653]: master offset -47 s2 freq +2390 path delay
46595
ptp4l[531.656]: master offset -551 s2 freq +1872 path delay
46551
ptp4l[532.659]: master offset 139 s2 freq +2397 path delay
46551
ptp4l[532.934]: caught signal 15


HTH,
Post by Richard Cochran
Richard
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