Also, in the log from the third ptp4l in the 07-latereselect test I
noticed a large negative path delay around second 106, it might be
worth investigation too.

Suggestions/patches/bug reports are welcome.

(my todo list includes writing tests of the various PI servo options,
support for multiple interfaces for boundary clocks and per-port delay
generator configuration to make it easier to reproduce some of the
sync/fup reorder bugs)